Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a wafer test operation of a semiconductor device.
As is well known, some tests may be performed in mass production or R&D (research and development) of semiconductor devices such as a dynamic random access memory (DRAM). Such tests include a product test, which is performed by detecting defects in fabrication processes such as a wafer process or assembly process to remove failed products, and a verification test, which verifies whether the semiconductor devices work normally in accordance with the design specification.
After the semiconductor device is fabricated, a test may be performed to determine pass/fail with respect to all cells of the semiconductor device. Cells which can be repaired among the failed cells are repaired, and the cells which cannot be repaired are discarded.
Such a test includes a screening test which sorts out failed DRAMs at a wafer level of the semiconductor devices.
In general, the screening test detects fail of semiconductor devices by performing a probing test using a probe at a wafer level in the course of the production of semiconductor devices.
In the probing test, a plurality of semiconductor devices existing on a wafer may be tested at the same time.
A channel refers to the minimum number of input/output pins necessary for testing the respective semiconductor devices existing on the wafer. If the number of channels per the semiconductor device existing on the wafer increases, the number of probes necessary for the wafer test increases. Thus, the number of semiconductor devices testable at a time decreases, and time necessary for the screening test increases.
On the other hand, if the number of channels per the semiconductor device existing on the wafer decreases, the number of probes used for the wafer test decreases. Thus, the number of semiconductor devices testable at a time increases, and time necessary for the screening test decreases.
Therefore, since a small number of channels per the semiconductor device exist on the wafer, an efficiency of screening test may increase.
FIG. 1 is a block diagram illustrating a usage of a reset signal input pad in a known semiconductor device.
Referring to FIG. 1, a semiconductor device buffers a signal EXT_RESET applied through a reset signal input pad RESET_PAD, and generates an internal reset signal INT_RESETB.
That is, the signal EXT_RESET applied through the reset signal input pad RESET_PAD is used for the purpose of generating the internal reset signal INT_RESETB.
Since it is difficult to predict when to reset the semiconductor device in a normal operation, it is apparent that the signal EXT_RESET applied through the reset signal input pad RESET_PAD is used only for the purpose of generating the internal reset signal INT_RESETB.
However, when the screening test is performed on the semiconductor device at the wafer level, the semiconductor device need not be reset any more if the semiconductor device is reset once in the early test operation.
Therefore, in the screening test of the semiconductor device at the wafer level, if the internal reset signal INT_RESETB is activated in the early test operation and resets the semiconductor device, a deactivated state is maintained.
According to the semiconductor device of FIG. 1, however, when the screening test is performed on the semiconductor device at the wafer level, even though the operation of changing the logic level of the internal reset signal INT_RESET by using the signal EXT_RESET applied through the reset signal input pad RESET_PAD is performed only in the early test operation, since the reset signal input pad RESET_PAD is used only for the purpose of generating the internal reset signal INT_RESETB, inefficiency follows.
Although it may be a small loss with respect to an individual semiconductor device, it is not a small loss in that a large number of semiconductor devices are tested at a time in the screening test at the wafer level.